1. Field of the Invention
The present invention relates generally to wireless packet communication, and more particularly, to a method and apparatus for enabling low-power communication by providing dual variable clocks optimized for physical layer execution parts and upper layer execution parts, respectively, in a wireless packet communication system.
2. Discussion of Related Art
Most of the electric power consumed in a CMOS (Complimentary Metal Oxide Silicon) digital circuit is consumed by charging/discharging of a load capacitor. Here, since the electric power consumption is in linear proportion to a driving clock frequency, the driving clock frequency is preferably optimized in order to reduce the electric power consumption. In this regard, there is an optimal driving voltage for an optimal driving clock frequency. Thus, low-power processors capable of varying driving voltage and frequency, such as Crusoe of Transmeta, 405LP of IBM, XScale and newest Mobile Pentium of Intel etc., have been released onto the market.
Conventional art related to the present invention includes technology related to ASICs (Application-specific integrated circuits) including a clock control capable of dynamically varying frequency according to a data throughput of a mobile device (U.S. Pat. No. 6,564,329 B1), technology related to a control system for varying a CPU clock speed according to a processing request of a device when a predetermined application program is executed or a predetermined interrupt is serviced (Korean Patent Publication No. 2001-099880), technology related to a method for controlling a CPU clock speed designed to reduce electric power consumption by varying the CPU clock speed according to an operational mode of a system operating system (Korean Patent Publication No. 2004-076678), research related to a MAC (Media Access Control) layer processing structure and a bus structure which are capable of performing power management making the most of battery characteristics (Communications, 2002, ICC 2002, IEE International Conference on Volume: 2 pp. 669-674, vol. 2), and research related to accomplishing lower power consumption (Solid-State Circuits, IEE Journal of Volume: 38, PP. 2001-2009).
Wireless packet communication devices based on wireless access protocol standards such as Bluetooth (IEEE 802.15.1), WLAN (IEEE 802.11a/b/g), WiMAX (IEEE 802.16d/e), etc. support multiple transfer modes (e.g. in the case of an IEEE 802.11g based system, eight transfer modes of 6, 9, 12, 18, 24, 36, 48 and 54 Mbps) and packet retransmission function.
In general, a wireless packet communication device supporting the multiple transfer modes parses a header of a received packet, thereby operating in any one of a plurality of transfer modes defined in a protocol prescribed in each standard, wherein the operated transfer mode is suitable for a radio environment. For example, when the radio environment deteriorates, the wireless communication device switches into a low transmission rate transfer mode and operates in a low transmission rate. In this case, a clock frequency provided to guarantee a high transmission rate is inefficient for the low transmission rate transfer mode in terms of electric power consumption.
Meanwhile, when the other party does not receive a previously transmitted packet, the wireless communication device retransmits the missing packet. Here, an actual data transmission rate can be lower than a predicted data transmission rate in the transfer mode. For example, if an IEEE 802.11g based wireless communication device, which can support the eight transfer modes of 6, 9, 12, 18, 24, 36, 48 and 54 Mbps, operates in the 18 Mbps transfer mode, the actual transmission rate is 13 Mbps. In this case, the driving clock frequency optimal for the transfer mode of 18 Mbps is used and thus electric power is unnecessarily consumed.